This invention generally relates to the programming of programmable integrated circuit structures; and more specifically, the invention relates to the connecting of antifuses to connect elements in an array of logic elements.
Elements for programming PROM""s, EEPROM""s and logic arrays have included fuses and transistors. It is also possible to make programmable connections using shortable elements referred to as antifuses. An antifuse is an element that before programming has a high impedance and after application of an appropriate voltage, changes to a low impedance conductive state. A thin dielectric, such as silicon dioxide, between two conductive regions, such as aluminum, can serve as an antifuse, programmable by the current and local heat that occurs when sufficient voltage is applied to cause current to flow through the dielectric.
A three dimensional wiring option is available with some antifuse structures by nature of the layout shown in FIG. 1, which shows a cross-sectional drawing of an electrically programmable antifuse cell structure 10 presently used. The antifuse cell includes an array capacitor that has one of the two terminals contacted to a buried N-band.
The remaining terminal is accessed through an N+ source/drain diffusion. In the unprogrammed state, the capacitor is an open circuit. In the programed state, the cell dielectric has been ruptured by an electrical overvoltage and a connective filament exists between the two plates of the capacitor.
With reference to FIG. 2, in order to program a unique fuse, a programming transistor T1 is incorporated into the antifuse/fuse latch circuit. When programming a unique antifuse, programming transistor T1 needs to be selected by a decoding scheme.
FIG. 3 shows the wiring, generally referenced at 30, associated with a conventional decoding scheme. The example in FIG. 3 portrays 4 antifuse and latch banks, with each bank including 9 antifuse/fuse latch circuits. Thus, there are a total of 36 programming transistors that need to be uniquely selected by the decoding circuit. In FIG. 3, a total of 36 interconnect lines are used to select one of 36 programming transistors. The layout of these antifuse/fuse latch circuits are interconnect limited.
An object of this invention is to reduce the number of wires needed for electrical decoding of electronic fuse banks thereby reducing complexity and layout area.
Another object of the present invention is to program antifuses in parallel.
A further object of this invention is to provide an antifuse bank structure that reduces the number of wires needed for electrical decoding and that, at the same time, also allows antifuses to be programmed in parallel.
These and other objectives are attained with an antifuse array, comprising a plurality of antifuse elements and a plurality of cell plates. Each of the antifuse elements comprises a programming transistor and one of the cell plates. The programming transistor and the cell plate of each antifuse element are both activated to program the antifuse element. Each of the cell plates is coupled to a portion of the plurality of antifuse elements and to one of a plurality of decode circuits, and the decode circuits selectively activate its coupled cell plate.
With a preferred embodiment, a multitude of interconnect lines are connected to the antifuses, and in particular, each interconnect line intersects each of the cell plates and is associated with one antifuse in each group of antifuses. With this preferred embodiment, the array of antifuses are decoded by predecoding one of the cell plates by elevating the cell plate which has been at ground voltage to a program voltage, and decoding one of the interconnect lines to program one of the antifuses. The intersection of the cell plate set to the program voltage and the decoded interconnect line results in programming a unique antifuse.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.